The invention described herein is particularly useful in a data processing system of the type wherein a memory controller controls a plurality of memory devices organized for storing multi-byte memory words. In such a memory error detection and correction syndrome bits are generated typically over a number of bytes of the memory word such as, for example, four bytes of a 32-bit memory word.
When a central processor unit (CPU) writes a word of data to such a memory the error syndrome bits are generated for the entire word and stored within associated memory devices. However, when the CPU writes less than a full word of data, such as a byte (eight bits) or a half word (16 bits) of data, the memory controller operates to first read the full word of data, merge the byte or bytes, generate the error syndrome bits over the full merged word and write the merged word with the associated syndrome bits back to memory. As can be appreciated, this read/modify/write type of access may be a time consuming process.
In some systems a plurality of CPUs are coupled to a common system bus and, through the system bus, to one or more memory units. Each CPU may have a local cache memory wherein a copy of a portion of a main system memory is maintained. In such a system it is a desirable goal that the main memory be updated to accurately reflect changes made to data within the cache memories. For example, such a system may employ a write-through type of cache memory wherein data written to the cache is also written "through" the cache to the main memory. For this purpose a first-in/first-out (FIFO) memory can be employed in parallel with the cache, the FIFO accepting write data from the CPU and temporarily buffering the data before providing the data over a system bus to the main memory. The FIFO is normally a word width or greater.
For those write operations of less than a word in width the data stored within the FIFO reflects the result of a read/modify/write type of access wherein a byte or half word is already merged by the CPU with a cache word. Thus, instead of writing a byte or half word to the memory and incurring the read/modify/write cycle time delay in generating the error syndrome bits, a more efficient cache memory write-through technique writes a full, already merged word from the FIFO to the memory.
However, a problem is created when another system bus agent, such as another CPU in a multi-processor system, writes to the main memory during the interval of time that the word of data is temporarily buffered within the FIFO. In this case the word in main memory that is the target of the FIFO may have just been updated by the other bus agent. Permitting the full word to be written from the FIFO would result in the newer data being over-written by the older data contained within the FIFO and the destruction in the main memory of the newer data.
It is thus one object of the invention to provide a method and apparatus for updating data within a main memory as a result of a write operation to a local cache memory.
It is another object of the invention to provide a method and apparatus for use with a write-through cache that updates data within a main memory by providing a dual port memory, such as a FIFO buffer, in parallel with the cache memory and to further provide circuitry for detecting when a write occurs to the main memory to invalidate a full word write of data from the FIFO buffer to the main memory.
It is a further object of the invention to provide a method and apparatus for use with a write-through cache that updates data within a main memory by providing a FIFO buffer in parallel with the cache memory and to further provide circuitry for detecting when a write occurs to the main memory and circuitry to modify an associated memory command from a word write access to less than a word type of write access to prevent data in the main memory from being overwritten with possibly non-current data.